Electron transport in low-dimensional structures, such as nanowires, nanotubes and quantum dots, is important not only for fundamental scientific research but is increasingly relevant to future advances in electronics and photonics. These materials have extraordinary electronic, optical, thermal, mechanical and chemical properties and could be used in a wide range of nanotechnologies from biomedical to quantum-functional devices for next-generation nano-electronics. Semiconductor nanowires (NWs) are a promising approach to future electronics as the limits to traditional scaling of silicon (Si)-integrated circuits approaches.
Researchers at the University of New Mexico have developed a very simple, but radically innovative approach to growing and—importantly—to positing ioning massive arrays of nanowires. Distinguished Professor Emeritus Dr. Steven Brueck and Research Associate Professor Seung-Chang Lee from the Department of Electrical & Computer Engineering and the Center for High Technology Materials have developed a method for catalyst-free epitaxy of single-material NWs or vapor-liquid-solid (VLS) epitaxy for complementary dual-material NWs with two different metal catalysts spatially separated on predetermined local (111) facets for single-direction growth on a Si (001) substrate. (VLS nanowires typically grow perpendicular to their substrates, which makes organizing and contacting them into circuits difficult and complex.) Epitaxy refers to the process of depositing a crystalline layer, or film, on a crystalline substrate and is used to grow defect-free semiconductors and nanomaterials.
The nanowires can be bent elastically so that the upper parts of individual nanowires physically contact nearby Si(001) substrate surfaces allowing planar processing (the dominant approach to manufacturing integrated circuits) with co-planar contacts, such as conventional Si complementary metal-oxide semiconductors (CMOS), and efficiently create high-density/high-current tunnel field effect transistors (TFETs) through segmentation of a single nanowire leading to a serial/parallel array of sub-nanowires. Using this approach of sequential growth of NWs with off-site planar doping, the inventors have envisioned gate-all-around (GAA) NW C-TEFTs on a single Si substrate oriented to (001) for high integration density and large drain current.
Researchers are increasingly interested in integrating indium arsenide (InAs) and related NW materials in transistors as the conduction material in next generation electronics due to the material’s high electron mobility as compared to silicon. In particular, TFETs are emerging as potential replacements for CMOS transistors for their extremely low switching power consumption and low off currents. Although several TFETs with different materials and fabrication technologies have been reported, most of them are conceptual and thus practically incompatible with future Si nano-electronics as a result of material qualities degraded in epitaxy, low-yield processing, and/or a substrate orientation different from (001), the orientation of the mainstream Si industry.
This invention resolves most of these issues with epitaxial NWs on Si (001) that allow in-plane gate-all-around (GAA) NW TFETs with well-matured CMOS planar process technology. They can compete with any conventional planar/vertical field effect transistors (FETs) in current Si microelectronics in production yield and integration density. Furthermore, doping control that is a problematic issue in any NW devices can be resolved simply by in-situ doping using standard planar processes. This is very important to complementary (C-) function of TFETs which require nm-scale heavy p- and n-type doping profiles for high tunneling current. The well-matured planar processing established on Si (001) is directly applicable to these NWs.
The technology has widespread applications in many areas, including use in integrated circuits (specifically transistors), semiconductors, electronic and optoelectronic devices, nanoelectromechanical devices, optics, and biomedical devices. It is an ultimate solution for NW devices because the radical innovation process reliably produces TFETs with high integration density and high current. Additionally, no pick-up and relocation of individual NWs is necessary, which is typically required when manufacturing NW devices, and the NWs are bendable to the substrate with minimal stress and controlled manipulation.
STC has filed patent application(s) on this exciting new technology and is currently examining commercialization options. If you are interested in information about this or other UNM technologies, please contact Arlene Mirabal at email@example.com or 505-272-7886.